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LCD Level Shifters with VCOM, NRS Buffers, and High Voltage Edge Detector ADSY8401
FEATURES
Complete suite of level shifters Eight inverting and three complementary level shifters for LCD timing High voltage edge detector Integrated low offset buffer for VCOM drives high capacitive loads MUXed input, low offset buffer for 2-level precharge drives high capacitive loads High current buffer for precharge provides high current drive into large capacitive loads Low power dissipation: 576 mW Available in 48-lead 7 mm x 7 mm LFCSP E-pad
DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11
FUNCTIONAL BLOCK DIAGRAM
DVCC AVCCL AVCC
ADSY8401
8 8
DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9T DO10T DO11T DO9C DO10C DO11C
3 3 3
R
PRODUCT DESCRIPTION
The ADSY8401 provides fast, 3 V to 15 V level shifters for LCD panel timing signals. An integrated low offset analog buffer is capable of driving the high capacitive loads. A 2:1 MUX input, low offset buffer simplifies application of 2-level precharge signals. A high current buffer provides high slew rates for large capacitive loads. The ADSY8401 is fabricated on ADI's fast, 26 V XFHV process, providing fast input logic, high voltage level shifters, and precision drive amplifiers on the same chip. The ADSY8401 dissipates 576 mW nominal static power. The ADSY8401 is offered in a 48-lead 7 mm x 7 mm LFCSP E-pad package and operates over the commercial temperature range of 0C to 85C.
DTCTI S
DTCTO
+1 AMPI
AMPO
SEL MUXA MUXB +1 MUXO
+1 BFRI GSW DGND AGNDL AGND
BFRO
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
04758-0-001
ADSY8401 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 Maximum Power Dissipation ..................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Amplifier Applications..................................................................... 8 Amp Section as VCOM Buffer ................................................... 8 MUX and BFR Sections as NRS Buffer ..................................... 8 MUX Section as VCOM Buffer .................................................. 8 Level Shifter Characteristics............................................................ 9 Level Shifter Timing Characteristics ......................................... 9 Inverting and Complementary Level Shifter Timing .............. 9 Level Shifting Edge Detector Timing Characteristics ........... 10 Level Shifting Edge Detector Timing ...................................... 10 Applications..................................................................................... 11 AMP Channel ............................................................................. 11 MUX Channel............................................................................. 11 Driving NRS................................................................................ 11 BFR Channel ............................................................................... 11 Grounded Output Mode ........................................................... 11 Driving VCOM ........................................................................... 11 PCB Design for Optimized Thermal Performance ............... 13 Power Supply Sequencing ......................................................... 14 Layout Considerations............................................................... 14 Total Power Dissipation............................................................. 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
7/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADSY8401 SPECIFICATIONS
At 25C, AVCC = AVCCL = 15.5 V, DVCC = 3.3 V, TA min = 0C, TA max = 85C, unless otherwise noted. Table 1.
Parameter Amp Section INPUT/OUTPUT CHARACTERISTICS Voltage Range VH VL Output Voltage Grounded Mode Input Current Output Current Output Offset Voltage Output Offset Voltage PSRR Gain Error OUTPUT DYNAMIC PERFORMANCE -3 dB Bandwidth (Small Signal) Slew Rate Settling Time to 0.5% Overshoot MUX Section INPUT/OUTPUT CHARACTERISTICS Voltage Range VH VL Output Voltage Grounded Mode Input Current II MUXA, MUXB Output Current Output Offset Voltage Output Offset Voltage PSRR Gain Error SEL INPUT CHARACTERISTICS IIH SEL IIL SEL VTH SEL VIH SEL VIL SEL OUTPUT DYNAMIC PERFORMANCE -3 dB Bandwidth (Small Signal) Slew Rate Settling Time to 0.5% Overshoot OUTPUT DYNAMIC PERFORMANCE -3 dB Bandwidth (Small Signal) Slew Rate Settling Time to 0.5% Overshoot Conditions Min Typ Max Unit
AVCC - VH VL - AGND GSW = LOW
VAMPI = 6 V, TA = 25C VAMPI = 6 V, TA min to TA max AVCC 10%, TA min to TA max VAMPI = 3 V to 10 V, TA min to TA max TA min to TA max, VO = 5 V step, CL = 1 nF VO = 0.25 V p-p TA min to TA max
1.5 1.1 45 100 20 1.5 0.1 0.07 5.2 13 0.5 0.05
2.5 1.5
8 11 0.12
V V mV nA mA mV mV mV/V % MHz V/s s %
1
AVCC - VH VL - AGND GSW = LOW
1.5 1.1 45 100 20 1.5 0.1 0.07 0.05 -0.7 1.65 2
2.5 1.5
V V mV nA mA mV mV mV/V % A A V V V MHz V/s s % MHz V/s s %
VMUXA, B = 7.5 V, TA = 25C VMUXA, B = 7.5 V, TA min to TA max AVCC 10%, TA min to TA max VMUXA, B 1.5 V to 12 V, TA min to TA max
8 11 0.12
0.8 VO = 5 V step, CL = 1 nF VO = 0.25 V p-p TA min to TA max VO = 5 V step, CL = 15 pF VO = 0.25 V p-p TA min to TA max 5.2 13 0.5 0.05 27 13 0.4 0.1
1
0.7
Rev. 0 | Page 3 of 16
ADSY8401
Parameter BFR Section INPUT/OUTPUT CHARACTERISTICS Voltage Range VH VL Output Voltage Grounded Mode Input Current Output Current Output Offset Voltage Output Offset Voltage PSRR, TA min to TA max Gain Error, TA min to TA max OUTPUT DYNAMIC PERFORMANCE -3 dB Bandwidth (Small Signal) Slew Rate Settling Time to 0.5% Overshoot MUX and BFR Sections as NRS Buffer Settling Time to 0.5% Level Shifter Section LEVEL SHIFTER LOGIC INPUTS CIN IIH IIL VIH VIL VTH LEVEL SHIFTER OUTPUTS VOH VOL LEVEL SHIFTER DYNAMIC PERFORMANCE Output Rise, Fall Times, tr, tf DO1-DO8, DO9T-DO11T, DO9C-DO11C DO1-DO8 Propagation Delay times, t11, t12, t13, t14 DO1-DO8, DO9T-DO11T, DO9C-DO11C DO1-DO8 Propagation Delay Skew, t15, t16 DO1-DO8 Propagation Delay Skew, t15, t16, t17, t18 DO1-DO8, DO9T-DO11T, DO9C-DO11C Conditions Min Typ Max Unit
AVCC - VH VL - AGND GSW = LOW
BFRI = 7.5 V, TA = 25C BFRI = 7.5 V, TA min to TA max AVCC 10% BFRI = 1.5 V to 12 V VO = 6 V step, CL = 10 nF VO = 0.25 V p-p TA min to TA max See Figure 4 CL = 10 nF
1.5 1.1 90 0.3 100 6 1 0.5 1.3 12 0.7 0.3 0.9
2.5 1.5
20 30 0.65
V V mV A mA mV mV mV/V % MHz V/s s % s
1
1.5
3 0.05 -0.6 2 0.8 1.65 AVCCL - 0.5 TA min to TA max 10% to 90% CL = 40 pF CL = 300 pF CL = 40 pF CL = 300 pF CL = 40 pF CL = 40 pF 4 AVCCL - 0.25 0.25
pF A A V V V V V
0.5
20 130 23 60
30 150 50 80 2
ns ns ns ns ns ns
Rev. 0 | Page 4 of 16
ADSY8401
Parameter Level Shifting Edge Detector Section Input Low Voltage, VIL Input High Voltage, VIH Input Rising Edge Threshold Voltage, VTH LH Input Falling Edge Threshold Voltage, VTH HL Output High Voltage, VOH Output Low Voltage, VOL Input Current High State, IIH Input Current, IIL Input Rising Edge Propagation Delay Time, t19 Input Falling Edge Propagation Delay Time, t20 t20 Variation with Temperature, t20 Output Rise, Fall Time, tr Grounded-Mode Switch GSW INPUT CHARACTERISTICS CIN RIN IIH IIL VIH VIL VTH Power Supplies Operating Range, DVCC Quiescent Current, DVCC Operating Range, AVCC, AVCCL1, 2, 3 Quiescent Current, AVCCL1 Quiescent Current, AVCCL2 Quiescent Current, AVCCL3 Quiescent Current, AVCCL2 Quiescent Current, AVCCL3 Quiescent Current, AVCC Operating Temperature Ambient Temperature Range, TA Conditions CL = 10 pF Min Typ Max AGND + 1.5 AVCC - 1.5 AGND + 3 AVCC - 3 DVCC - 0.25 0.25 1.2 -1.2 15.5 16.5 2 6 Unit V V V V V V A A ns ns ns ns
DVCC - 0.5
0.5 2.5
-2.5
TA = 25C to 85C 10% to 90%
3 50 0.6 -70 2 0.8 1.65 3 3.3 20 12.5 5.2 5.2 11.5 11.5 10 0 3.6 25 18 15.5 6.6 6.6 14.3 14.3 12.8 85
pF k A A V V V V mA V mA mA mA mA mA mA C
DI1 - DI11 VIL DI1 - DI11 VIL DI1 - DI11 VIH DI1 - DI11 VIH
In still air
Rev. 0 | Page 5 of 16
ADSY8401 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameters Supply Voltages AVCC to AGND AVCCL to AGNDL AGND to AGNDL AGND to DGND DVCC to DGND Input Voltages Maximum Digital Input Voltages Minimum Digital Input Voltages Maximum Analog Input Voltages Minimum Analog Input Voltages Internal Power Dissipation1 LFCSP Package at 25C, Ambient Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 10 s) Rating 18 V 18 V 0.5 V 0.5 V 4.5 V DVCC + 0.5 V DGND - 0.5 V AVCCx + 0.5 V AGNDx - 0.5 V 3.8 W 0C to 85C -65C to +125C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
MAXIMUM POWER DISSIPATION
Junction Temperature
The maximum power that can be safely dissipated by the ADSY8401 is limited by its junction temperature. The maximum safe junction temperature for plastic encapsulated devices as determined by the glass transition temperature of the plastic is approximately 150C. Exceeding this limit temporarily might cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 150C for an extended period can result in device failure.
1
48-lead LFCSP package: JA = 26C/W (still air): JEDEC STD, 4-layer PCB, 0 CFM airflow JC = 20C/W JB =11.0C/W (still air) JT =0.4C/W (still air)
Exposed Paddle
The die paddle must be in good thermal contact with at least a partial plane for proper operation in high ambient temperature environments. The partial plane must be in good electrical contact with AVCC or AGND for reliable electrical operation. See the PCB Design for Optimized Thermal Performance section for more information on the use of the exposed paddles to dissipate excess heat.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 6 of 16
ADSY8401 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DTCTO MUXO
48 47 46 45 44 43 42 41 40 39 38 37
DVCC 1 GSW 2 SEL 3 AGNDL 4 DO9T 5 DO9C 6 DO10T 7 DO10C 8 DO11T 9 DO11C 10 AVCCL1 11 DI11 12
AMPO
MUXB
MUXA
DGND
AGND
DTCTI
AVCC
BFRO
AMPI
BFRI
36 35 34 33 32
AVCCL3 DO1 DO2 DO3 DO4 AGNDL AVCCL2 DO5 DO6 DO7 DO8 AGNDL
ADSY8401
TOP VIEW (Not to Scale)
31 30 29 28 27 26 25
13
14
15
16
17
18
19
20
21
22
23
24
04758-0-002
DI9
DI8
DI7
DI6
DI5
DI4
DI3
DI2
DI10
DVCC
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1, 18 2 Mnemonic DVCC GSW Description Digital Power Supply. Grounded Mode Switch. When the voltage on the GSW pin is tied to DGND, the AMPO, MUXO, and BFRO outputs are pulled to near AGND. When the GSW input is left unconnected or tied to DVCC, all outputs operate normally. The level shifters are not affected by the GSW input. Analog Precharge. Low offset unity gain amplifier with MUXed inputs. Drives large capacitive loads. For driving large capacitive loads at high slew rates, connect MUXO to BFRI and the load capacitance to BFRO. SEL = HIGH selects MUXA. Level Shifter Ground. Complementary Level Shifter Outputs. While the corresponding input voltage of these level shifters is below the threshold voltage, the voltage at the noninverting output pins is at VOL and the voltage at the inverting outputs is at VOH. While the corresponding input voltage of these level shifters is above the threshold voltage, the voltage at the noninverting output pins is at VOH and the voltage at the inverting outputs is at VOL. Level Shifter Power Supply. Complementary Level Shifter Inputs. Low voltage input of the complementary level shifters. Inverting Level Shifter Inputs. Low voltage input of the inverting level shifters. Digital Ground. This pin is normally connected to the digital ground plane. Inverting Level Shifter Outputs. While the corresponding input voltage of these level shifters is below the threshold voltage, the output voltage at these pins is at VOH. While the corresponding input voltage of these level shifters is above the threshold voltage, the output voltage at these pins is at VOL. Analog Amplifier. Low offset unity gain amplifier. Drives large capacitive loads such as VCOM. Analog Buffer. High current output buffer. Analog Power Supplies. Analog power supplies for the level shifter and the amplifiers. Analog Supply Returns. Analog supply returns for the level shifter and the amplifiers. Edge Detecting Level Shifter Output. Logic output of the inverting level shifting edge detector. Edge Detecting Level Shifter Input. High voltage input of the inverting level shifting edge detector.
3, 39-41
SEL, MUXA, MUXB, MUXO
4, 25, 31 5-10
AGNDL DO9-11T, DO9-11C
11, 30, 36 12-14 15-17, 20-24 19, 47 26-29, 32-35 37-38 42, 44 43 45 46 48
AVCCL1, 2, 3 DI9-11 DI1-8 DGND DO1-8
AMPO, AMPI BFRI, BFRO AVCC AGND DTCTO DTCTI
Rev. 0 | Page 7 of 16
DGND
DI1
ADSY8401 AMPLIFIER APPLICATIONS
AMP SECTION AS VCOM BUFFER
AMPO
+1
VCOMI GSW
VCOM
04758-0-003
Figure 3. Amp Section as VCOM Buffer
MUX AND BFR SECTIONS AS NRS BUFFER
SEL NRSA NRSB
GSW
GSW
BFRO
MUXO
+1
NRS
+1
BFRI
04758-0-004
Figure 4. MUX and BFR Sections as NRS Buffer
MUX SECTION AS VCOM BUFFER
MUXO
+1
VCOMI
VCOM
04758-0-005
GSW
Figure 5. MUX Section as VCOM Buffer
Rev. 0 | Page 8 of 16
ADSY8401 LEVEL SHIFTER CHARACTERISTICS
LEVEL SHIFTER TIMING CHARACTERISTICS
DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8
DI9 DI10 DI11
DO9T DO10T DO11T DO9C DO10C DO11C
INVERTING
COMPLEMENTARY
Figure 6. Level Shifter Timing Characteristics
INVERTING AND COMPLEMENTARY LEVEL SHIFTER TIMING
INPUTS
t11
INVERTING OUTPUTS
t12
t15 t17
NONINVERTING OUTPUTS
04758-0-006
t16 t18
04758-0-007
t13
t14
Figure 7. Inverting and Complementary Level Shifter Timing
Table 4.
Parameter LEVEL SHIFTER SECTION Output Rise, Fall Times, tr, tf DO1-DO8, DO9T-DO11T, DO9C-DO11C DO1-DO8 Propagation Delay times, t11, t12, t13, t14 DO1-DO8, DO9T-DO11T, DO9C-DO11C DO1-DO8 Propagation Delay Skew, t15, t16 DO1-DO8 Propagation Delay Skew, t15, t16, t17, t18 DO1-DO8 to DO9T-DO11T and DO9C-DO11C Conditions TA min to TA max CL = 40 pF CL = 300 pF CL = 40 pF CL = 300 pF CL = 40 pF CL = 40 pF 4 ns Min Typ Max Unit
20 130 23 60
30 150 50 80 2
ns ns ns ns ns
Rev. 0 | Page 9 of 16
ADSY8401
LEVEL SHIFTING EDGE DETECTOR TIMING CHARACTERISTICS
S
04758-0-008
DTCTI R
DTCTO
Figure 8. Level Shifting Edge Detector Timing Characteristics
LEVEL SHIFTING EDGE DETECTOR TIMING
AVCCL DTCTI AGNDL DVCC DTCTO DGND
t19
t20
04758-0-009
Figure 9. Level Shifting Edge Detector Timing
Table 5.
Parameter LEVEL SHIFTING EDGE DECTECTOR Input Low Voltage, VIL Input High Voltage, VIH Input Rising Edge Threshold Voltage, VTH LH Input Falling Edge Threshold Voltage, VTH HL Output High Voltage, VOH Output Low Voltage, VOL Input Current High State, IIH Input Current, IIL Input Rising Edge Propagation Delay Time, t19 Input Falling Edge Propagation Delay Time, t20 t20 Variation with Temperature, t20 Output Rise, Fall Time, tr Conditions CL = 10 pF Min Typ Max
AGND + 1.5
AVCC - 1.5
AGND + 3 AVCC - 3 DVCC - 0.25 0.25 1.2 -1.2 15.5 16.5 2 6
Unit
V V V V V V A A ns ns ns ns
DVCC - 0.5
0.5 2.5
-2.5
TA = 25C to 85C
Rev. 0 | Page 10 of 16
ADSY8401 APPLICATIONS
The ADSY8401 is designed as part of a DecDriver(R) based LCD driver platform. The level shifters provide an interface between the image processor and a timing loop, operating at 3.3 V, and the LCD with high voltage timing input levels. The edge detecting level shifter provides an interface between the LCD monitor output at high voltage and a timing loop such as the AD8389 at 3.3 V. Low offset buffers, AMP and MUX, are capable of driving high capacitive loads such as VCOM and NRS without additional buffering. The high current buffer BFR is capable of 100 mA output current, providing high slew rates into large capacitive loads, which are often required for the precharge input, NRS of LCDs.
BFR CHANNEL
The BFR channel comprises a high output current buffer. It can be used to increase the output drive capability of either the AMP or MUX channels. The BFR channel is most often used in series with the MUX channel output to realize a high current drive NRS switch.
GROUNDED OUTPUT MODE
In certain designs it is desirable to pull the amplifier and buffer outputs to near ground during power-down. When the voltage on the GSW pin is tied to DGND, the AMPO, MUXO, and BFRO outputs are pulled to near AGND. When the GSW input is left unconnected or tied to DVCC, all outputs operate normally. The level shifters are not affected by the GSW input.
AMP CHANNEL
The AMP channel is a low offset unity gain buffer designed to drive a wide range of capacitive loads with a clean settling response. In LCD panel applications, it is most frequently used as a VCOM buffer.
DRIVING VCOM
The AMP channel comprises a low offset, unity gain buffer. It can be used to drive a large capacitive load, such as VCOM, directly with low overshoot. In certain systems, it might be desirable for a single ADSY8401 to drive the VCOM inputs of more than one LCD panel. In such cases, the MUX channel can be used to drive VCOM directly. The MUX's switching function is not used, and its output is tied directly to VCOM without the use of the BFR channel. Offset errors and pulse response are the same as that of the AMP channel.
MUX CHANNEL
The MUX channel is a 2-input, buffered analog multiplexer. The overall performance of its buffered output is very similar to that of the AMP channel. It is ideally suited for driving a wide range of capacitive loads, from very small up to several nF.
DRIVING NRS
Analog voltage switching capability is provided by the MUX channel. To achieve rapid settling while driving the capacitive NRS input, the output of the MUX is buffered by the high current drive BFR channel.
AD8381/AD8382/AD8383
REFERENCE VOLTAGES VRH, VRL, V1, V2 DB(0:9/11) STSQ, XFR, CLK, R/L, INV VID(0:6) 6
LCD
IMAGE PROCESSOR
10/12
ADSY8401
DY, DIRY, NRG DIRX, CLX,CLY DI1-DI8 DO1-DO4 DO5-DO8 ENBX(1-4) DX, DY, DIRY, NRG
1/3 AD8389
DXI, CLXI, ENBX(1-4)I CLK ENBX(1-4)xO DXxO CLXxO MONITxI VCOM DI9-DI11 DTCTO AMPI BFRI NRS1 NRS2 INV MUXA MUXB SEL
DO9T-DO11T, DO9C-DO11C DTCTI AMPO BFRO MUXO
CLX, CLXN CLY, CLYN DIRX MONITOR VCOM NRS
04758-0-010
Figure 10. Typical Application--One ADSY8401 per Color
Rev. 0 | Page 11 of 16
ADSY8401
IMAGE PROCESSOR
ENBXR(1:4) ENBXB(1:4) CLXR, CLYRB CLXB DI1-DI4 DI5-DI8 DI9-DI10 DO9T-DO9C DI11 DO10T-DO10C DO11T, DO11C CLX, CLXN CLY, CLYN DIRX DO1-DO4 DO5-DO8
RED LCD
ENBX(1-4) DX DY DIRY
BLUE LCD
ENBX(1-4) DX DY DIRY CLX, CLXN CLY, CLYN DO1-DO4 ENBXG(1:4) DX, DY, DIRY DVCC DIRX CLXG, CLYG DI1-DI4 DI5-DI7 DI8 DI9 DI10-DI11 DO5 DO6 DO7 DO8 DO9T DO9C DO10T-DO11T DO11T-DO11C DIRX
GREEN LCD
ENBX(1-4) DX DY DIRY CLX, CLXN, CLY, CLYN DIRX
04758-0-011
Figure 11. Typical Application--Two ADSY8401 per System, Level Shifters
ADSY8401
VCOMR NRSA NRSB SEL AMPI BFRI MUXA MUXB SEL AMPO BFRO MUXO
RED LCD
VCOM NRS
BLUE LCD
VCOM NRS
ADSY8401
VCOMG DC INPUT ~ AVCC/2 VCOMB DVCC AMPI BFRI MUXA MUXB SEL AMPO BFRO MUXO
GREEN LCD
VCOM NRS
04758-0-012
Figure 12. Typical Application--Two ADSY8401 per System, Amplifiers
Rev. 0 | Page 12 of 16
ADSY8401
PCB DESIGN FOR OPTIMIZED THERMAL PERFORMANCE
The total maximum power dissipation of the ADSY8401 is partly load-dependent. In a typical 60 Hz XGA system, the total maximum power dissipation is 1 W. The ADSY8401 package is designed to provide superior thermal characteristics, partly through the exposed die paddle on the bottom surface of the package. To take full advantage of this feature, the exposed paddle must be in direct thermal contact with the PCB, which then serves as a heat sink. A thermally effective PCB must incorporate a thermal pad and a thermal via structure. The thermal pad provides a solderable contact surface on the top surface of the PCB. The thermal via structure provides a thermal path to the inner and bottom layers of the PCB to remove heat.
Solder Masking
To minimize the formation of solder voids due to solder flowing into the via holes (solder wicking), the via diameter should be small. Solder masking of the via holes on the top layer of the PCB plugs the via holes, inhibiting solder flow into the holes. To optimize the thermal pad coverage, the solder mask diameter should be no more than 0.1 mm larger than the via diameter. Table 7. Recommended Solder Mask Dimensions
Solder Mask Top layer Pads Thermal vias Bottom layer Dimensions Set by customer's PCB design rules 0.25 mm diameter circular mask centered on the vias Set by customer's PCB design rules
Thermal Pad Design
To minimize thermal performance degradation of production PCBs, the contact area between the thermal pad and the PCB should be maximized. Therefore, the size of the thermal pad on the top PCB layer should match the exposed paddle. The second thermal pad of the same size should be placed on the bottom side of the PCB. At least one thermal pad should be in direct thermal contact with an external plane such as AVCC or GND.
7mm
Thermal Via Structure Design
Effective heat transfer from the top to the inner and bottom layers of the PCB requires thermal vias incorporated into the thermal pad design. Thermal performance increases logarithmically with the number of vias. Near optimum thermal performance of production PCBs is attained only when tightly spaced thermal vias are placed on the full extent of the thermal pad. Table 6. Recommended Land Pattern Dimensions
Land Pattern Top and Bottom Layers Pad size Pad pitch Thermal pad size Thermal via structure Dimensions 0.5 mm x 0.25 mm 0.5 mm 5.25 mm x 5.25 mm 0.25 mm diameter vias on 0.5 mm grid
7mm
LAND PATTERN-TOP LAYER LAND PATTERN-BOTTOM LAYER
Thermal Pad and Thermal Via Connections
Thermal pads are connected to the AGND or AVCC plane. The thermal pad on the solder side is connected to a plane. The use of thermal spokes is not recommended when connecting the thermal pads or via structure to the plane.
04758-0-013
SOLDER MASK-TOP LAYER
Figure 13. PCB Layers
Rev. 0 | Page 13 of 16
ADSY8401
POWER SUPPLY SEQUENCING
As indicated in the Absolute Maximum Ratings section, the voltage at any input pin cannot exceed its supply voltage by more than 0.5 V. To ensure compliance with the absolute maximum ratings, power-up and power-down sequencing might be required. During power-up, initial application of nonzero voltages to any of the input pins must be delayed until the supply voltage ramps up to at least the highest maximum operational input voltage. During power-down, the voltage at any input pin must reach zero during a period not exceeding the hold-up time of the power supply. Failure to comply with the absolute maximum ratings may result in functional failure or damage to the internal ESD diodes. Damaged ESD diodes can cause temporary parametric failures, which can result in image artifacts. Damaged ESD diodes cannot provide full ESD protection, reducing reliability. Power-on sequence: 1. 2. Apply power to supplies. Apply inputs.
Layout and Grounding
The analog outputs and the digital inputs of the ADSY8401 are on opposite sides of the package. Keep these sections separated to minimize crosstalk and coupling of digital inputs into the analog outputs. All signal trace lengths should be made as short and direct as possible to prevent signal degradation due to parasitic effects. Note that a digital signal should not cross or be routed near analog signals. It is imperative to provide a solid analog ground plane under and around the ADSY8401. All ground pins of the part should be connected directly to this ground plane with no extra signal path length. This includes AGND, AGNDL, and DGND. The return traces for any of the signals should be routed close to the ground pin for that section to prevent stray signals from coupling into other ground pins.
Power Supply Bypassing
All power supply pins of the ADSY8401 must be properly bypassed to the analog ground plane for optimum performance.
TOTAL POWER DISSIPATION
The total power dissipation of the ADSY8401 has three components: * * Quiescent power dissipation when all digital inputs are low. Dynamic power dissipation due to the capacitance of the LCD (typical CL = 200 pF for all the NRG control inputs, CL = 40 pF for all other control inputs). Average power dissipation due to the toggling inputs.
Power-off sequence: 1. 2. Remove signal from inputs. Remove power from supplies.
Power-Off Sequencing Using the GSW Pin
In certain designs it is desirable to pull the amplifier, buffer, and level shifter outputs to near ground during power-down. Power-off sequence with GSW: 1. 2. 3. 4. 5. Apply low to the GSW pin. Apply high to all level shifter input pins. Pull the MUXA, MUXB, AMPI, and BFRI inputs to AGND. Remove AVCC. Remove DVCC. *
When DI1-DI11 are at digital low, the quiescent power dissipation of the ADSY8401 is 576 mW. When DI1-DI11 are at digital high, the quiescent power dissipation is 771 mW. The typical dynamic power dissipation of each of the three ADSY8401, due to the capacitance of the LCD, is 155 mW in a typical 60 Hz XGA system, shown in Figure 10. It is 304 mW and 153 mW, respectively, for the two ADSY8401s in the 60 Hz XGA system shown in Figure 11. The average power dissipation of each of the three ADSY8401 due to DI1-DI11 toggling is 23 mW in the system shown in Figure 10. It is 32 mW and 22 mW, respectively, for the two ADSY8401 in the system shown in Figure 11. The total power dissipation of each of the three ADSY8401 in the XGA system, shown in Figure 10, is 754 mW. The total power dissipation of the two ADSY8401s in the XGA system, shown in Figure 12, is 912 mW and 751 mW, respectively.
LAYOUT CONSIDERATIONS
The ADSY8401 is a mixed-signal, high speed, high accuracy device. To fully realize its specifications, it is essential to use a properly designed printed circuit board.
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ADSY8401 OUTLINE DIMENSIONS
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48
PIN 1 INDICATOR
1
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
BOTTOM VIEW
5.25 5.10 SQ 4.95
0.50 0.40 0.30
25 24
12 13
0.25 MIN 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 5.50 REF
1.00 0.85 0.80
12 MAX
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 14. 48-Lead Lead Frame Chip Scale Package [LFCSP] (CP-48) Dimensions shown in millimeters
ORDERING GUIDE
Model ADSYS8401JPCZ1 Temperature Range 0C to 85C Package Description Lead Frame Chip Scale Package Package Option CP-48
1
Z = Pb-free part.
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ADSY8401 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04758-0-7/04(0)
Rev. 0 | Page 16 of 16

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